Rockchip64: Add verisilion av1 patches

config/kernel/linux-rockchip64-current.config

@@ -7,6 +7,7 @@ CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_BPF_SYSCALL=y
 CONFIG_BPF_JIT=y
+CONFIG_BPF_JIT_ALWAYS_ON=y
 # CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
 CONFIG_BPF_LSM=y
 CONFIG_PREEMPT=y
@@ -25,6 +26,7 @@ CONFIG_IKCONFIG_PROC=y
 CONFIG_IKHEADERS=m
 CONFIG_LOG_BUF_SHIFT=18
 CONFIG_NUMA_BALANCING=y
+CONFIG_CGROUP_FAVOR_DYNMODS=y
 CONFIG_MEMCG=y
 CONFIG_BLK_CGROUP=y
 CONFIG_CFS_BANDWIDTH=y
@@ -90,6 +92,7 @@ CONFIG_BLK_DEV_ZONED=y
 CONFIG_BLK_DEV_THROTTLING=y
 CONFIG_BLK_WBT=y
 CONFIG_BLK_CGROUP_IOLATENCY=y
+CONFIG_BLK_CGROUP_IOCOST=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_MISC=m
 CONFIG_ZSWAP=y
@@ -513,6 +516,7 @@ CONFIG_MPLS_IPTUNNEL=m
 CONFIG_HSR=m
 CONFIG_QRTR_TUN=m
 CONFIG_CGROUP_NET_PRIO=y
+CONFIG_BPF_STREAM_PARSER=y
 CONFIG_NET_PKTGEN=m
 CONFIG_NET_DROP_MONITOR=m
 CONFIG_HAMRADIO=y
@@ -2815,6 +2819,7 @@ CONFIG_ARM_SMMU_V3_SVA=y
 CONFIG_IOMMUFD=m
 CONFIG_ROCKCHIP_IOMMU=y
 CONFIG_VIRTIO_IOMMU=m
+CONFIG_VSI_IOMMU=y
 CONFIG_LITEX_SOC_CONTROLLER=m
 CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_DEVFREQ_GOV_PERFORMANCE=m
@@ -3409,6 +3414,7 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_MEMORY_INIT=y
 CONFIG_TEST_LOCKUP=m
 CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_FUNCTION_TRACER=y
 CONFIG_FTRACE_SYSCALLS=y
 CONFIG_BPF_KPROBE_OVERRIDE=y
 CONFIG_KUNIT=m

config/kernel/linux-rockchip64-edge.config

@@ -2833,6 +2833,7 @@ CONFIG_ARM_SMMU_V3_SVA=y
 CONFIG_IOMMUFD=m
 CONFIG_ROCKCHIP_IOMMU=y
 CONFIG_VIRTIO_IOMMU=m
+CONFIG_VSI_IOMMU=y
 CONFIG_LITEX_SOC_CONTROLLER=m
 CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_DEVFREQ_GOV_PERFORMANCE=m

patch/kernel/archive/rockchip64-6.18/media-0005-media-verisilicon-AV1-Set-IDR-flag-for-intra_only-fr.patch

@@ -0,0 +1,31 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Benjamin Gaignard <[email protected]>
+Date: Thu, 8 Jan 2026 10:56:28 +0100
+Subject: media: verisilicon: AV1: Set IDR flag for intra_only frame type
+
+Intra_only frame could be considered as a key frame so
+Instantaneous Decoding Refresh (IDR) flag must be set of the both
+case and not only for key frames.
+
+Signed-off-by: Benjamin Gaignard <[email protected]>
+Fixes: 727a400686a2c ("media: verisilicon: Add Rockchip AV1 decoder")
+---
+ drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
+index 111111111111..222222222222 100644
+--- a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
++++ b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
+@@ -1995,7 +1995,7 @@ static void rockchip_vpu981_av1_dec_set_parameters(struct hantro_ctx *ctx)
+ 			 !!(ctrls->frame->quantization.flags
+ 			    & V4L2_AV1_QUANTIZATION_FLAG_DELTA_Q_PRESENT));
+
+-	hantro_reg_write(vpu, &av1_idr_pic_e, !ctrls->frame->frame_type);
++	hantro_reg_write(vpu, &av1_idr_pic_e, IS_INTRA(ctrls->frame->frame_type));
+ 	hantro_reg_write(vpu, &av1_quant_base_qindex, ctrls->frame->quantization.base_q_idx);
+ 	hantro_reg_write(vpu, &av1_bit_depth_y_minus8, ctx->bit_depth - 8);
+ 	hantro_reg_write(vpu, &av1_bit_depth_c_minus8, ctx->bit_depth - 8);
+-- 
+Armbian
+

patch/kernel/archive/rockchip64-6.18/media-0006-media-verisilicon-AV1-Fix-tx-mode-bit-setting.patch

@@ -0,0 +1,78 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Benjamin Gaignard <[email protected]>
+Date: Tue, 9 Dec 2025 11:34:17 +0100
+Subject: media: verisilicon: AV1: Fix tx mode bit setting
+
+AV1 specification describes 3 possibles tx modes: 4x4 only,
+largest and select.
+Hardware allows 5 possibles tx modes: 4x4 only, 8x8, 16x16,
+32x32 and select.
+Since the both aren't exactly matching we need to add a mapping
+function to set the correct mode on hardware.
+
+Signed-off-by: Benjamin Gaignard <[email protected]>
+Fixes: 727a400686a2c ("media: verisilicon: Add Rockchip AV1 decoder")
+---
+ drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c | 27 +++++++++-
+ 1 file changed, 26 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
+index 111111111111..222222222222 100644
+--- a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
++++ b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
+@@ -72,6 +72,14 @@
+ 		: AV1_DIV_ROUND_UP_POW2((_value_), (_n_)));		\
+ })
+
++enum rockchip_av1_tx_mode {
++	ROCKCHIP_AV1_TX_MODE_ONLY_4X4	= 0,
++	ROCKCHIP_AV1_TX_MODE_8X8	= 1,
++	ROCKCHIP_AV1_TX_MODE_16x16	= 2,
++	ROCKCHIP_AV1_TX_MODE_32x32	= 3,
++	ROCKCHIP_AV1_TX_MODE_SELECT	= 4,
++};
++
+ struct rockchip_av1_film_grain {
+ 	u8 scaling_lut_y[256];
+ 	u8 scaling_lut_cb[256];
+@@ -1935,11 +1943,26 @@ static void rockchip_vpu981_av1_dec_set_reference_frames(struct hantro_ctx *ctx)
+ 	rockchip_vpu981_av1_dec_set_other_frames(ctx);
+ }
+
++static int rockchip_vpu981_av1_get_hardware_tx_mode(enum v4l2_av1_tx_mode tx_mode)
++{
++	switch (tx_mode) {
++	case V4L2_AV1_TX_MODE_ONLY_4X4:
++		return ROCKCHIP_AV1_TX_MODE_ONLY_4X4;
++	case V4L2_AV1_TX_MODE_LARGEST:
++		return ROCKCHIP_AV1_TX_MODE_32x32;
++	case V4L2_AV1_TX_MODE_SELECT:
++		return ROCKCHIP_AV1_TX_MODE_SELECT;
++	}
++
++	return ROCKCHIP_AV1_TX_MODE_32x32;
++}
++
+ static void rockchip_vpu981_av1_dec_set_parameters(struct hantro_ctx *ctx)
+ {
+ 	struct hantro_dev *vpu = ctx->dev;
+ 	struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
+ 	struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
++	int tx_mode;
+
+ 	hantro_reg_write(vpu, &av1_skip_mode,
+ 			 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_SKIP_MODE_PRESENT));
+@@ -2005,7 +2028,9 @@ static void rockchip_vpu981_av1_dec_set_parameters(struct hantro_ctx *ctx)
+ 			 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_HIGH_PRECISION_MV));
+ 	hantro_reg_write(vpu, &av1_comp_pred_mode,
+ 			 (ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_REFERENCE_SELECT) ? 2 : 0);
+-	hantro_reg_write(vpu, &av1_transform_mode, (ctrls->frame->tx_mode == 1) ? 3 : 4);
++
++	tx_mode = rockchip_vpu981_av1_get_hardware_tx_mode(ctrls->frame->tx_mode);
++	hantro_reg_write(vpu, &av1_transform_mode, tx_mode);
+ 	hantro_reg_write(vpu, &av1_max_cb_size,
+ 			 (ctrls->sequence->flags
+ 			  & V4L2_AV1_SEQUENCE_FLAG_USE_128X128_SUPERBLOCK) ? 7 : 6);
+-- 
+Armbian
+